Compiler infrastructures are often an area of high interest for research. As the necessityfor digital information and technology increases, so does the need for an increase in theperformance of digital hardware. The main component in most complex digital systems isthe central processing unit (CPU). Compilers are responsible for translating code writtenin a high-level programming language to a sequence of instructions that is then executedby the CPU. Most research in compiler technologies is focused on the design and optimization of the code written by the programmer; however, at some point in this processthe code must be converted to instructions specific to the CPU. This paper presents thedesign of a simplified CPU architecture as well as the less understood side of compilers:the backend, which is responsible for the CPU instruction generation. The CPU design isa 32-bit reduced instruction set computer (RISC) and is written in Verilog. Unlike mostembedded-style RISC architectures, which have a compiler port for GCC (The GNU Compiler Collection), this compiler backend was written for the LLVM compiler infrastructureproject. Code generated from the LLVM backend is successfully simulated on the customCPU with Cadence Incisive, and the CPU is synthesized using Synopsys Design Compiler.