摘要翻译：
由于polar码具有可证明的容量实现性能，近年来引起了广泛的研究兴趣。为了获得良好的纠错性能，采用大列表长度的列表逐次对消译码(LSCD)对极性码进行译码。然而，随着列表规模的增加，列表管理操作的复杂度和延迟迅速增加，导致LSCD的总时延变大，限制了polar码在高吞吐量和时延敏感应用中的适用性。因此，本文研究了大列表LSCD的低延迟实现。具体来说，在系统级，提出了一种选择性扩展方法，使得一些可靠比特不被扩展，以减少计算量和延迟。在算法层次上，提出了一种基于双阈值的快速近似排序方法，以减少大列表的LSCD时延。在此基础上，提出了一种实现选择性扩展和双阈值方案的LSCD的VLSI结构，并采用UMC 90 nm CMOS工艺实现。实验结果表明，在时钟频率为658 MHz的情况下，即使对于16个大的链表，所提出的LSCD也能获得460 Mbps的译码吞吐量。
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英文标题：
《A Low-Latency List Successive-Cancellation Decoding Implementation for
  Polar Codes》
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作者：
YouZhe Fan, ChenYang Xia, Ji Chen, Chi-Ying Tsui, Jie Jin, Hui Shen,
  Bin Li
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最新提交年份：
2018
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分类信息：

一级分类：Computer Science        计算机科学
二级分类：Information Theory        信息论
分类描述：Covers theoretical and experimental aspects of information theory and coding. Includes material in ACM Subject Class E.4 and intersects with H.1.1.
涵盖信息论和编码的理论和实验方面。包括ACM学科类E.4中的材料，并与H.1.1有交集。
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一级分类：Computer Science        计算机科学
二级分类：Hardware Architecture        硬件体系结构
分类描述：Covers systems organization and hardware architecture. Roughly includes material in ACM Subject Classes C.0, C.1, and C.5.
涵盖系统组织和硬件架构。大致包括ACM主题课程C.0、C.1和C.5中的材料。
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一级分类：Electrical Engineering and Systems Science        电气工程与系统科学
二级分类：Signal Processing        信号处理
分类描述：Theory, algorithms, performance analysis and applications of signal and data analysis, including physical modeling, processing, detection and parameter estimation, learning, mining, retrieval, and information extraction. The term "signal" includes speech, audio, sonar, radar, geophysical, physiological, (bio-) medical, image, video, and multimodal natural and man-made signals, including communication signals and data. Topics of interest include: statistical signal processing, spectral estimation and system identification; filter design, adaptive filtering / stochastic learning; (compressive) sampling, sensing, and transform-domain methods including fast algorithms; signal processing for machine learning and machine learning for signal processing applications; in-network and graph signal processing; convex and nonconvex optimization methods for signal processing applications; radar, sonar, and sensor array beamforming and direction finding; communications signal processing; low power, multi-core and system-on-chip signal processing; sensing, communication, analysis and optimization for cyber-physical systems such as power grids and the Internet of Things.
信号和数据分析的理论、算法、性能分析和应用，包括物理建模、处理、检测和参数估计、学习、挖掘、检索和信息提取。“信号”一词包括语音、音频、声纳、雷达、地球物理、生理、（生物）医学、图像、视频和多模态自然和人为信号，包括通信信号和数据。感兴趣的主题包括：统计信号处理、谱估计和系统辨识；滤波器设计；自适应滤波/随机学习；（压缩）采样、传感和变换域方法，包括快速算法；用于机器学习的信号处理和用于信号处理应用的机器学习；网络与图形信号处理；信号处理中的凸和非凸优化方法；雷达、声纳和传感器阵列波束形成和测向；通信信号处理；低功耗、多核、片上系统信号处理；信息物理系统的传感、通信、分析和优化，如电网和物联网。
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一级分类：Mathematics        数学
二级分类：Information Theory        信息论
分类描述：math.IT is an alias for cs.IT. Covers theoretical and experimental aspects of information theory and coding.
它是cs.it的别名。涵盖信息论和编码的理论和实验方面。
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英文摘要：
  Due to their provably capacity-achieving performance, polar codes have attracted a lot of research interest recently. For a good error-correcting performance, list successive-cancellation decoding (LSCD) with large list size is used to decode polar codes. However, as the complexity and delay of the list management operation rapidly increase with the list size, the overall latency of LSCD becomes large and limits the applicability of polar codes in high-throughput and latency-sensitive applications. Therefore, in this work, the low-latency implementation for LSCD with large list size is studied. Specifically, at the system level, a selective expansion method is proposed such that some of the reliable bits are not expanded to reduce the computation and latency. At the algorithmic level, a double thresholding scheme is proposed as a fast approximate-sorting method for the list management operation to reduce the LSCD latency for large list size. A VLSI architecture of the LSCD implementing the selective expansion and double thresholding scheme is then developed, and implemented using a UMC 90 nm CMOS technology. Experimental results show that, even for a large list size of 16, the proposed LSCD achieves a decoding throughput of 460 Mbps at a clock frequency of 658 MHz.
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PDF链接：
https://arxiv.org/pdf/1806.11301