Unlimited Vector Extension (UVE) is a novel ISA extension that incorporates data streaming and scalablevectorization. To do so, it implements a data streaming engine that allows detaching the main memoryaccess from computation, releasing some pressure from the main pipeline of the processor. This isdone by statically encoding the memory access pattern of streamable loops through a set of specialdescription instructions, to offload the corresponding address sequence generation to the streamingengine. This not only allows the computational code to be simplified by removing memory addressinginstructions,but also simplifies the vectorization of the loop, in turn increasing the throughput of theprocessing cores. However a new extension that implements target specific instructions, it still lackscompiler support to produce target code. Accordingly, in this thesis aims at taking the first steps in thedevelopment of a compiler for UVE by instantiating a new subtarget from RISC-V’s LLVM backend andcreating and encoding the extension’s instructions. To provide an initial integration with LLVM IR, a setof intrinsics is also proposed that match the instructions. Due to the intrinsic incompatibility betweenthe streaming paradigm from UVE and LLVM IR SSA form, a new approach to overcome this issue isintroduced based on pseudo-instructions . The new backend and LLVM IR intrinsics were evaluated witha set of benchmarks that highlight the main introduced features