摘要翻译：
无线通信的需求促使通信系统向高性能方向发展。然而，影响通信性能的主要瓶颈是快速傅立叶变换(FFT)，它是大多数调制器的核心。本文提出了一种FFT结构的流水线数字切片、无乘法器基22、DIF（频率抽取）、SDF（单路径延迟反馈）蝶形的FPGA实现方法。为了降低蝶形乘法器的计算复杂度，在流水线基22 DIF SDF FFT结构的关键路径上采用了数字切片无乘法器技术。提出的设计着重于芯片实现的速度和有源硅面积之间的权衡。将乘法器输入的数据分成四个块，每个块有四个位，同时并行处理。对新的体系结构进行了研究，并用MATLAB软件进行了仿真。在Xilinx ISE环境下导出了描述FFT蝶形功能的Verilog HDL代码，并下载到Virtex II FPGA板上。最后，利用Virtex-II FG456 Proto板在实际硬件上实现并测试了该设计。结果，综合报告表明，最大时钟频率555.75MHz，总等效门数32146比基22 DIF SDF FFT蝶形有明显的改善。与传统的蝶形结构设计只能工作在最大时钟频率200.102MHz和传统的乘法器只能工作在最大时钟频率221.140MHz相比，该系统显示了更好的结果。
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英文标题：
《FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2
  power of 2 DIF SDF Butterfly for Fourier Transform Structure》
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作者：
Yazan Samir Algnabi, Rozita Teymourzadeh, Masuri Othman, Md Shabiul
  Islam
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最新提交年份：
2018
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分类信息：

一级分类：Electrical Engineering and Systems Science        电气工程与系统科学
二级分类：Signal Processing        信号处理
分类描述：Theory, algorithms, performance analysis and applications of signal and data analysis, including physical modeling, processing, detection and parameter estimation, learning, mining, retrieval, and information extraction. The term "signal" includes speech, audio, sonar, radar, geophysical, physiological, (bio-) medical, image, video, and multimodal natural and man-made signals, including communication signals and data. Topics of interest include: statistical signal processing, spectral estimation and system identification; filter design, adaptive filtering / stochastic learning; (compressive) sampling, sensing, and transform-domain methods including fast algorithms; signal processing for machine learning and machine learning for signal processing applications; in-network and graph signal processing; convex and nonconvex optimization methods for signal processing applications; radar, sonar, and sensor array beamforming and direction finding; communications signal processing; low power, multi-core and system-on-chip signal processing; sensing, communication, analysis and optimization for cyber-physical systems such as power grids and the Internet of Things.
信号和数据分析的理论、算法、性能分析和应用，包括物理建模、处理、检测和参数估计、学习、挖掘、检索和信息提取。“信号”一词包括语音、音频、声纳、雷达、地球物理、生理、（生物）医学、图像、视频和多模态自然和人为信号，包括通信信号和数据。感兴趣的主题包括：统计信号处理、谱估计和系统辨识；滤波器设计；自适应滤波/随机学习；（压缩）采样、传感和变换域方法，包括快速算法；用于机器学习的信号处理和用于信号处理应用的机器学习；网络与图形信号处理；信号处理中的凸和非凸优化方法；雷达、声纳和传感器阵列波束形成和测向；通信信号处理；低功耗、多核、片上系统信号处理；信息物理系统的传感、通信、分析和优化，如电网和物联网。
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一级分类：Computer Science        计算机科学
二级分类：Hardware Architecture        硬件体系结构
分类描述：Covers systems organization and hardware architecture. Roughly includes material in ACM Subject Classes C.0, C.1, and C.5.
涵盖系统组织和硬件架构。大致包括ACM主题课程C.0、C.1和C.5中的材料。
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英文摘要：
  The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This paper presents FPGA implementation of pipeline digit-slicing multiplier-less radix 22 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure. The approach is taken, in order to reduce computation complexity in butterfly multiplier, the digit-slicing multiplier-less technique was utilized in the critical path of pipeline Radix-22 DIF SDF FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The multiplier input data was sliced into four blocks each one with four bits to process at the same time in parallel. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 555.75 MHz with the total equivalent gate count of 32,146 is a marked and significant improvement over Radix 22 DIF SDF FFT butterfly. In comparison with the conventional butterfly architecture design which can only run at a maximum clock frequency of 200.102 MHz and the conventional multiplier can only run at a maximum clock frequency of 221.140 MHz, the proposed system exhibits better results.
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PDF链接：
https://arxiv.org/pdf/1806.0457